The present invention relates to a method for preventing poisoning of photoresist materials during patterning of low dielectric constant (xe2x80x9clow-kxe2x80x9d) materials which contain at least one constituent which can cause photoresist poisoning, such as nitrogen, or where the patterning process utilizes a nitrogen-based etching/ashing chemistry. The invention has particular applicability in the manufacture of high integration density, multi-metallization level semiconductor devices comprising accurately formed, sub-micron dimensioned features and interconnection patterns while exhibiting high circuit speeds due to reduced capacitance loading.
The escalating requirements for high integration density and performance associated with ultra-large scale (xe2x80x9cULSIxe2x80x9d) integration semiconductor device wiring and interconnection patterns are difficult to satisfy in terms of providing accurately dimensioned, sub-micron sized features (e.g., 0.18 xcexcm and below, such as 0.15 xcexcm and below). Moreover, interconnection technology is being constantly challenged to satisfy the ever-increasing requirements for high performance (e.g., circuit speed) associated with such ULSI devices. The circuit speed of such integrated circuit (xe2x80x9cICxe2x80x9d) devices varies inversely with the product of the resistance and capacitance of the interconnection system, i.e., the xe2x80x9cRC productxe2x80x9d. Thus, the higher the value of the RC product, the more limiting the circuit speed, and, as IC devices become more complex, with smaller feature sizes and spacings, the circuit speed becomes less dependent upon the component transistors, etc., and more dependent upon the interconnection pattern. As a consequence of the effect of the RC product upon circuit speed, at deep sub-micron regimes, e.g., less than about 0.12 xcexcm, the performance of multi-level interconnection patterns and systems becomes dominated by the interconnect capacitance. As a further consequence, the rejection rate of IC devices due to circuit speed delays arising from RC effects has become a limiting factor in IC fabrication.
Conventional semiconductor IC devices typically comprise a semiconductor substrate, such as a doped monocrystalline silicon (Si) wafer including a plurality of active device regions, e.g., transistors, formed therein or thereon, and a plurality of overlying, sequentially formed interlayer dielectrics (xe2x80x9cILDxe2x80x9ds) and electrically conductive patterns, e.g., of metal. An IC is formed therefrom containing a plurality of electrically conductive patterns comprising conductive lines separated by interwiring spaces, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of different layers, i.e., upper and lower vertically spaced-apart layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes an electrical contact with an active device region on or within the semiconductor substrate, such as a source or drain region of a transistor. Conductive lines are formed in trenches which typically extend substantially horizontally with respect to the semiconductor substrate. Semiconductor devices comprising five (5) or more levels of vertically interconnected metallization are becoming more prevalent as device geometries and feature sizes decrease into the deep sub-micron range.
In fabricating multi-metallization level devices such as described above, conductive plugs filling via openings for electrically interconnecting vertically spaced-apart metallization levels are typically formed by a process sequence comprising steps of: (1) depositing an inter-layer dielectric (ILD) on a patterned, electrically conductive layer, e.g., a metal layer comprising at least one metal feature; (2) forming a desired opening in the ILD, as by means of photolithographic masking and etching techniques, and filling the opening with a plug of an electrically conductive material, e.g., tungsten (W); and (3) removing excess conductive material deposited on the surface of the ILD during filling of the opening, as by chemical-mechanical polishing/planarization (xe2x80x9cCMPxe2x80x9d).
A commonly employed method for fabricating such electrically conductive vias for interconnecting vertically spaced-apart metallization levels is termed xe2x80x9cdamascenexe2x80x9d processing and, in essence, involves the formation of an opening in the ILD which is filled with the plug of electrically conductive material. xe2x80x9cDual-damascenexe2x80x9d processing techniques involve formation of an opening in an ILD which comprises a lower, narrower width contact or via opening section which communicates with an upper, wider trench opening section, followed by simultaneous filling of both the lower and upper sections of the opening with an electrically conductive material, typically a metal or metallic material, to simultaneously form a conductive via plug in integral communication with a conductive line.
As described above, the drive toward manufacture of ULSI semiconductor devices having decreased circuit and feature sizes well into the deep sub-micron range has necessitated a reduction in the RC product of the metallization systems. Thus, in an effort to reduce interconnect capacitance, dielectric materials having very low values of dielectric constant (permittivity) have been developed for use as ILD""s in IC metallization systems formed by, e.g., the above-described damascene techniques. As compared with dielectric materials heretofore utilized as ILD""s and having values of dielectric constant (xe2x80x9ckxe2x80x9d) in the range of from about 3.9 for dense silicon dioxide (SiO2) to greater than about 8 for deposited silicon nitride (SixNy), these newer xe2x80x9clow-kxe2x80x9d dielectric materials are characterized by values of dielectric constant k which are less than about 3.9, e.g., about 3.5 or below (where the value of k is one (1) for a vacuum).
One type of low-k material that has been extensively studied for use as ILD""s in metallization processing are flowable oxides which are, in essence, ceramic polymers, such as, for example, hydrogen silsesquioxane (xe2x80x9cHSQxe2x80x9d). Such materials have been considered for use as xe2x80x9cgap-fillxe2x80x9d between spaced-apart metal lines in view of their flowability and ability to fill very small openings. Other possible low-k ILD materials with k values from about 2.0 to about 3.8 include FLARE 2.0(trademark), a poly(arylene)ether (available from Advanced Microelectronic Materials Division, Allied-Signal, Sunnyvale, Calif.); Black Diamond (trademark) (available from Applied Materials, Santa Clara, Calif.); BCB (divinylsiloxane bis-benzocyclobutene), FOx,(trademark) (HSQ-based), XLK(trademark) (HSQ-based), and SiLK(trademark), an aromatic hydrocarbon polymer (each available from Dow Chemical Co., Midland, Mich.); Coral(trademark), a carbon-doped silicon oxide (available from Novellus Systems, San Jose, Calif.); HOSP(trademark), a hybrid siloxane-organic polymer, and Nanoglass(trademark), a nanoporous silica (each available from Honeywell Electronic Materials); and halogen-doped (e.g., fluorine-doped) silicon dioxide derived from tetraethyl orthosilicate (TEOS) and fluorine-doped silicate glass (FSG).
A drawback associated with the use of the above-described damascene technology for forming sub-micron dimensioned in-laid metallization patterns and features, particularly in the case of xe2x80x9cvia first-trench lastxe2x80x9d type dual-damascene processing, arises from a phenomenon known as xe2x80x9cphotoresist poisoningxe2x80x9d, wherein a relatively narrow via opening is formed to extend completely through at least one ILD in a first anisotropic etching process utilizing a first patterned photoresist, and a relatively wide trench opening is formed in an upper portion of the via opening in a second anisotropic etching process utilizing a second patterned photoresist. According to such processing methodology, there is a tendency for contaminated photoresist material of the second photoresist utilized for trench opening formation to remain within the via opening in the at least one ILD after development and patterning of the second photoresist for trench mask formation for use in subsequent trench etching. The remaining contaminated photoresist may form a mushroom-shaped cap extending over only the mouth of the opening, or the contaminated photoresist may also at least partially fill the opening. In either instance, the remaining contaminated photoresist can adversely impact the dimensional accuracy of the subsequently formed trench, as will be explained below. Photoresist poisoning leading to loss of dimensional accuracy and control is particularly problematic when low-k dielectrics, such as are enumerated above, are utilized for the at least one ILD in via first-trench last dual-damascene processing.
FIG. 1 illustrates the above-described phenomenon, in which a semiconductor IC device structure 1 includes a lower metal feature 10, such as of copper (Cu) or Cu-based alloy, formed in a dielectric layer 11 overlying a semiconductor substrate (not shown in the figure for illustrative simplicity), typically a doped monocrystalline Si wafer including at least one active device or region formed thereon or therein, and a protective capping layer 12, such as of a silicon nitride, is formed thereon. A laminate comprising, in sequence from the capping layer 12, a first, or lower, low-k dielectric (ILD) layer 13, a middle etch stop layer 14, and a second, or upper, low-k dielectric (ILD) layer 15 is then formed over the capping layer 12. According to the via first-trench last processing sequence, a relatively narrow via opening or hole 16 is then formed to extend through the second, or upper ILD 15, the middle etch stop layer 14, and first, or lower ILD 13, terminating at the capping layer 12, by means of a first anisotropic etching process (typically reactive plasma etching) utilizing a first patterned photoresist layer as an etch mask and a first etch chemistry. The first patterned photoresist layer is then removed, for example, by a plasma ashing process utilizing an oxygen (O2) or nitrogen (N2) plasma. A second photoresist layer 17 is then formed over the second, or upper ILD 15, a portion of which is included within the via opening or hole 16. Photolithographic patterning of the second photoresist layer 17, including selective radiation exposure, development, and etching, is then performed to effect selective removal of photoresist portion 17A shown in phantom. However, due to the above-mentioned photoresist poisoning phenomenon, contaminated photoresist material 17B having a mushroom-shaped upper or cap portion 17C may remain within at least the upper part of the via opening or hole 16 and covering the portion of the second, or upper ILD 15 surrounding the perimeter of the mouth of the via opening or hole 16. As a consequence of the presence of the mushroom-shaped cap portion 17C partially overlying the upper surface of the second, or upper ILD 15, the subsequent anisotropic, reactive plasma etching process terminating at the middle, etch stop layer 14 for forming the trench may lead to poor transference of the desired pattern of the photoresist layer 17 to the upper ILD 15.
The generally accepted mechanism for occurrence of photoresist poisoning leading to mushroom-shaped via cap formation is as follows: during photolithographic patterning of the photoresist layer to form a mask pattern therein, a pattern of incident light or radiation from a radiation source travels through the photo-reactive polymeric material of the photoresist (xe2x80x9cPRxe2x80x9d) layer and is progressively absorbed as it photo-initiates reaction in the pattern of exposed areas. Contaminants which are incompatible with the photo-reactive polymer material can migrate into the photoresist layer from a bordering layer or enter the photoresist layer by other means and poison the photoresist material. For example, the contaminants can undergo interfering reactions with the photoresist material, causing non-uniformity of the photo-reaction therein by extraneous chemical reaction with the polymeric material. This phenomenon is known as photoresist poisoning and can lead to the formation of, e.g., the mushroom-shaped cap 17C overlying the mouth of the narrow width via opening or hole 16, as well as a portion of the upper surface of the upper ILD 15 surrounding the perimeter of the via opening or hole. In addition, the patterned areas of the photoresist layer may have non-uniform (i.e., non-vertical) sidewalls. In either case, subsequent etching utilizing such photoresist patterns as etch masks leads to imperfect transfer of the photoresist pattern to the underlying ILD layer(s), and ultimately limits the minimum spatial resolution since the etched structure is imprecise compared to the desired IC design.
Experimentation and investigation has determined that the most likely cause of photoresist poisoning associated with the use of low-k ILD""s, e.g., as in the above-described via first-trench last, dual-damascene processing for forming metallization patterns of ULSI semiconductor devices, is migration of reactive nitrogenous species from the low-k ILD materials (i.e., layers 13 and 15 in FIG. 1) into the layer (17) of photoresist material utilized for forming the trench, which nitrogenous species reacts therewith causing non-uniformity of the photo-initiated reaction by extraneous chemical interaction with the polymeric photoresist material. Further studies have suggested that the reactive nitrogenous species migrating from the ILD""s 13 and/or 15 is (are) derived from the low-k dielectric material(s) per se and/or from the introduction of nitrogenous species into such low k dielectric material(s) during steps of etching for formation of the via opening or hole 16 and/or for removal of the photoresist mask utilized in forming the via hole or opening 16, either or both of which steps may utilize a nitrogen-based or nitrogen-containing etching chemistry. (As employed in the specification and appended claims, the term xe2x80x9creactive nitrogenous speciesxe2x80x9d contemplates reactive nitrogen-containing substances including both nitrogen itself and attendant self-generating contaminant compounds thereof with other contaminating precursor constituents such as hydrogen, i.e., reactive nitrogen-containing contaminant compounds).
As design rules extend further into the sub-micron range, e.g., about 0.18 xcexcm and below, such as 0.15 xcexcm and below, for example, 0.12 xcexcm, and the number of metallization levels increases, necessitating a corresponding increase in the number of photoresist mask patterning and etching steps for forming recesses in low-k ILD""s, such as via openings, trenches, grooves, etc., maintenance of the critical feature sizes or dimensions of the metallization/interconnect pattern becomes increasingly important. Accordingly, the problem of photoresist poisoning resulting from contamination thereof with reactive species, originating either from the ILD material per se or from the etchinglashing chemistry utilized in via etching and/or photoresist removal, and resulting in the loss of desired metallization feature sizes, dimensions, and/or geometries, requires resolution.
Thus, there exists a need for methodology enabling the formation of sub-micron-dimensioned metal vias, contacts, interconnection and routing members, etc., having desired features sizes, dimensions, and geometries with high reliability and performance, and at high product yield. Specifically, there exists a need for methodology for eliminating the problem of loss of desired feature dimensions due to photoresist poisoning associated with mask patterning of photoresists layers overlying or in the vicinity of low-k dielectric material layers, e.g., ILD""s forming part of a multi-level metallization system of ULSI semiconductor devices, which methodology is rapid, cost-effective, and avoids the drawbacks and disadvantages associated with the conventional patterning techniques.
The present invention, wherein the interior wall surfaces of an opening formed in at least one low-k ILD, e.g., a via opening or hole, are subjected to a post-treatment in a hydrogen (H2)-containing atmosphere for eliminating, or at least substantially reducing, the amount of nitrogenous species migrating therefrom into the photoresist layer, e.g., a thermal or plasma treatment, subsequent to plasma ashing removal of the patterned photoresist utilized for formation of the via opening or hole, effectively addresses and solves the need for improved methodology for forming sub-micron-dimensioned recesses in low-k dielectric layers, e.g., ILD""s. Further, the methodology provided by the present invention can be readily and easily implemented in cost-effective manner utilizing conventional thermal or plasma treatment apparatus. Finally, the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components.
An advantage of the present invention is a method for eliminating, or at least substantially reducing, photoresist poisoning during recess patterning of a material.
Another advantage of the present invention is a method for eliminating, or at least substantially reducing, photoresist poisoning during recess patterning of a low-k dielectric material for use in multi-level metallization processing of high integration density semiconductor IC devices.
Still another advantage of the present invention is a method of manufacturing a semiconductor device which eliminates, or substantially reduces photoresist poisoning during recess patterning of low-k dielectric layers forming part of a multi-level metallization system of such device.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of eliminating, or at least substantially reducing, photoresist poisoning during recess patterning of a layer of a material, comprising the sequential steps of:
(a) forming a first photoresist layer on an upper surface of the layer;
(b) patterning the first photoresist layer to include at least one opening therein having a first width;
(c) forming at least one first recess in the upper surface of the layer utilizing the patterned first photoresist layer as a mask, the at least one first recess having a first width substantially corresponding to the first width of the at least one opening in the first photoresist layer and extending for a first depth below the surface of the layer;
(d) removing the first photoresist layer;
(e) treating exposed surfaces of the layer to eliminate, or at least substantially reduce the amount of, at least one contaminant or constituent thereof which can poison a second photoresist layer subsequently formed in contact with the upper surface of the layer; and
(f) forming a second photoresist layer on the upper surface of the layer;
wherein poisoning of the second photoresist layer by entry thereinto of the at least one contaminant or constituent of the layer is eliminated or at least substantially reduced due to the surface treating of step (e).
According to an embodiment of the present invention, the method comprises the further steps of:
(g) patterning the second photoresist layer to form at least one opening therein, the at least one opening in the second photoresist layer being vertically aligned with the at least one first recess in the layer and having a second width greater than the first width; and
(h) forming at least one second recess in an upper portion of said layer utilizing the second patterned photoresist layer as a mask, the at least one second recess having a second width substantially corresponding to the second, greater width of the at least one opening in the second photoresist layer, the at least one second recess communicating with the at least one first recess and extending for a second depth below the surface of the layer, the second depth being less than the first depth.
In accordance with embodiments of the present invention, step (a) comprises forming the first photoresist layer on the surface of a layer comprised of at least one low-k dielectric material having a dielectric constant less than about 3.9, which dielectric layer may be comprised of a laminate of layers of low-k dielectric materials.
According to embodiments of the present invention, step (a) comprises forming the first photoresist layer on the surface of a laminate of layers each comprised of a low-k dielectric material selected from the group consisting of hydrogen silsesquioxane-based ceramic polymers, poly(arylene) ether-based organic polymers. benzocyclobutene-based materials, aromatic hydrocarbon-based polymers, carbon-doped silicon oxide, hybrid siloxane-organic polymers, nanoporous silica, halogendoped silicon dioxides obtained from tetraethyl orthosilicate, and fluorine-doped silica glasses.
In accordance with embodiments of the present invention, step (c) comprises forming the at least one first recess in the upper surface of the layer by an anisotropic etching process, e.g., anisotropic etching utilizing a reactive plasma; step (d) comprises removing the first photoresist layer by plasma ashing in a nitrogen-containing atmosphere; and step (e) comprises treating the exposed surfaces of the layer with hydrogen, e.g., by contacting the exposed surfaces with hydrogen (H2) gas at an elevated temperature or with a hydrogen plasma.
According to embodiments of the present invention, step (h) comprises forming the at least one second recess in the upper portion of the layer by an anisotropic etching process, e.g., reactive plasma etching, utilizing the patterned second photoresist layer as a mask, the etching terminating at an etch stop layer within the layer at the second depth below the surface.
According to another aspect of the present invention, a method of manufacturing a semiconductor device comprises the sequential steps of:
(a) providing a workpiece comprising:
(i) a semiconductor substrate including at least one active device region or component formed therein or thereon;
(ii) a dielectric layer overlying the semiconductor substrate and including at least one metal feature in-laid in an upper surface of the dielectric layer;
(iii) a thin capping layer formed over at least the upper surface of the at least one metal feature; and
(iv) an interlayer dielectric layer formed over the thin capping layer;
(b) forming a first photoresist layer on an upper surface of the interlayer dielectric layer;
(c) patterning the first photoresist layer to include at least one opening therein having a first width;
(d) forming at least one first recess in the upper surface of the interlayer dielectric layer utilizing the patterned first photoresist layer as a mask, the at least one first recess having a first width substantially corresponding to the first width of the at least one opening in the first photoresist layer and extending through the interlayer dielectric layer to the thin capping layer;
(e) removing the first photoresist layer;
(f) treating exposed surfaces of the interlayer dielectric layer to eliminate, or at least substantially reduce the amount of, at least one contaminant or constituent thereof which can poison a second photoresist layer subsequently formed on the upper surface of the interlayer dielectric layer;
(g) forming a second photoresist layer on the upper surface of the interlayer dielectric layer;
(h) patterning the second photoresist layer to form at least one opening therein, the at least one opening in the second photoresist layer being vertically aligned with the at least one first recess and having a second width greater than the first width; and
(i) forming at least one second recess extending partway through the interlayer dielectric layer, the second recess having a second width substantially corresponding to the second, greater width of the at least one opening in the second photoresist layer and communicating with the at least one first recess.
According to embodiments of the present invention, step (a) comprises providing a workpiece wherein the interlayer dielectric layer (iv) further includes:
(iv1) a first, lower interlayer dielectric layer formed over the thin capping layer;
(iv2) a thin etch stop layer formed over the first interlayer dielectric layer; and
(iv3) a second, upper interlayer dielectric layer formed over the thin etch stop layer.
In accordance with embodiments of the present invention, each of the first, lower and second, upper interlayer dielectric layers comprises a low-k dielectric material having a dielectric constant less than about 3.9 and is selected from the group consisting of hydrogen silsesquioxane-based ceramic polymers, poly(arylene) ether-based organic polymers, benzocyclobutene-based materials, aromatic hydrocarbon-based polymers, carbon-doped silicon oxide, hybrid siloxane-organic polymers, nanoporous silica, halogen-doped silicon dioxides obtained from tetraethyl orthosilicate, and fluorine-doped silica glasses;
step (e) comprises removing the first photoresist layer by plasma ashing in a nitrogen-containing atmosphere; and
step (f) comprises treating the exposed surfaces of the first and second interlayer dielectric layers to eliminate, or at least substantially reduce the amount of nitrogen thereon or thereat by contacting the surfaces with hydrogen (H2) gas at an elevated temperature or with a hydrogen plasma.
In accordance with embodiments of the present invention, step (d) comprises anisotropic etching utilizing a reactive plasma; and step (i) comprises anisotropic etching utilizing a reactive plasma and terminating etching of the at least one second recess at the thin etch stop layer.
According to further embodiments of the present invention, the method further comprises the steps of:
(j) removing the second photoresist layer;
(k) removing the thin capping layer overlying the upper surface of the at least one in-laid metal feature at the bottom of the at least one first recess; and
(l) filling the at least one first and the at least one second communicating recesses with a metal plug to form at least one electrically conductive via in contact with the at least one in-laid metal feature and at least one electrically conductive line in contact with the at least one electrically conductive via.
In accordance with a particular embodiment of the present invention, step (a) comprises providing a workpiece wherein the semiconductor substrate comprises silicon (Si), the at least one inlaid metal feature comprises copper (Cu) or a Cu-based alloy, and the thin capping layer comprises a silicon nitride or oxynitride.